Working of the Counter
Initially, all flip-flops are at 000. With the first clock pulse, the first flip-flop becomes 1, resulting in 001. The second pulse yields 010 as the first flip-flop resets and the second changes state. The third pulse makes the first flip-flop 1 again, reaching 011.
At the fourth pulse, both first and second flip-flops become 0, and the third becomes 1, leading to 100. On the fifth clock pulse, we reach 101. A NAND gate then resets the system to 000 by feeding its output to the clock pins.
Displaying Vowel: A
The circuit successfully displays the vowel 'A'. This stage demonstrates the initial output of our sequential logic, confirming the correct configuration for the first vowel.
Displaying Vowel: E
Following 'A', the circuit transitions to display 'E'. This step validates the sequential progression and the accurate state changes within the flip-flops.
Displaying Vowel: I
The display now shows 'I', indicating another successful state transition. Each vowel's display confirms the precise timing and logic implemented in our design.
Displaying Vowels: O & U
Displaying O
The circuit progresses to display 'O', showcasing the consistent functionality of the sequential logic.
Displaying U
Finally, 'U' is displayed, completing the sequence of vowels and demonstrating the full operational capability of the design.
ModelSim
The ModelSim code provides the behavioral description and testbench for simulating the sequential vowel display. This code was crucial for verifying the logic before hardware implementation. For Code, Please refer to Github